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?2013 fairchild semiconductor corporation 1 www.fairchildsemi.com FSB70625 rev. c0 FSB70625 motion spm? 7 series february 2014 FSB70625 motion spm ? 7 series features ? ul certified no. e209204 (ul1557) ? high performance pqfn package ? 250 v r ds(on) = 0.8 ?? max ? frfet mosfet 3-phase inverter with gate drivers and protection ? separate open-source pins from low-side mosfets for three-phase current-sensing ? active-high interface, works with 3.3 / 5 v logic, schmitt-trigger input ? optimized for low electromagnetic interference ? hvic temperature-sensing built-in for temperature monitoring ? hvic for gate driving with under-voltage protection and interlock function ? isolation rating: 1500 v rms / min. ? moisture sensitive level (msl) 3 ? rohs compliant application ? 3-phase inverter driver for small power ac motor drives related source ? an-9077 - motion spm ? 7 series user?s guide ? an-9078 - surface mount guidelines for motion spm? 7 series general description the FSB70625 is an advanced motion spm ? 7 module providing a fully-featured, high-performance inverter output stage for ac induction, bldc and pmsm motors. these modules integrate optimized gate drive of the built-in mosfets (frfet ? technology) to minimize emi and losses, while also providing multiple on-module protection features includ ing under-voltage lockouts, thermal monitoring, fault reporting and interlock function. the built-in one hvic translates the incoming logic-level gate inputs to the high-voltage, high-current drive signals required to properly drive the module's internal mosfets. separate open-souce mosfet terminals are available for each phase to support the widest variety of control algorithms. package marking & ordering information device marking device package reel size tape width quantity FSB70625 FSB70625 pqfn27a 13?? 24 mm 1000 units
FSB70625 motion spm? 7 series ?2013 fairchild semiconductor corporation 2 www.fairchildsemi.com FSB70625 rev. c0 absolute maximum ratings inverter part (each mosfet unless otherwise specified.) control part (each hvic unless otherwise specified.) total system 1st notes: 1. t cb is pad temperature of case bottom. 2. marking ? * ? is calculation value or design factor. symbol parameter conditions rating unit v dss drain-source voltage of each mosfet 250 v *i d 25 each mosfet drain current, continuous t cb = 25c (1st note 1) 6.9 a *i d 80 each mosfet drain current, continuous t cb = 80c 5.2 a *i dp each mosfet drain current, peak t cb = 25c, pw < 100 ? s 13.9 a *p d maximum power dissipation t cb = 25c, for each mosfet 81 w symbol parameter conditions rating unit v dd control supply voltage applied between v dd and com 20 v v bs high-side bias voltage applied between v b and v s 20 v v in input signal voltage applied between in and com -0.3 ~ v dd + 0.3 v v fo fault output supply voltage applied between fo and com -0.3 ~ v dd + 0.3 v i fo fault output current sink current fo pin 5 ma v csc current sensing input voltage applied between csc and com -0.3 ~ v dd + 0.3 v symbol parameter conditions rating unit t j operating junction temperature -40 ~ 150 c t stg storage temperature -40 ~ 125 c v iso isolation voltage 60 hz, sinusoidal, 1 minute, con- nection pins to heat sink plate 1500 v rms
FSB70625 motion spm? 7 series ?2013 fairchild semiconductor corporation 3 www.fairchildsemi.com FSB70625 rev. c0 pin descriptions figure 1. pin configuration and internal block diagram 1st notes: 4. source terminal of each low-side mosfet is not connected to supply ground or bias voltage ground inside motion spm ? 7 product. external connections should be made as indicated in figure 2. 5. the suffix -a pad is connected with same number pin. ex) 8 and 8a is connected inside. pin number pin name pin description 1 /fo fault output 2v ts voltage output of hvic temperature 3 cfod capacitor for duration of fault output 4 csc capacitor (low-pass filter) for short-circuit current detection input 5v dd supply bias voltage for ic and mosfets driving 6 in_uh signal input for high-side u phase 7 in_vh signal input for high-side v phase 8 (8a) com common supply ground 9 in_wh signal input for high-side w phase 10 in_ul signal input for low-side u phase 11 in_vl signal input for low-side v phase 12 in_wl signal input for low-side w phase 13 nu negative dc-link input for u phase 14 u output for u phase 15 nv negative dc-link input for v phase 16 v output for v phase 17 w output for w phase 18 nw negative dc-link input for w phase 19 v s(w) high-side bias voltage ground for w phase mosfet driving 20 p w positive dc-link input for w phase 21 p v positive dc-link input for v phase 22 p u positive dc-link input for u phase 23 (23a) v s(v) high-side bias voltage ground for v phase mosfet driving 24 (24a) v s(u) high-side bias voltage ground for u phase mosfet driving 25 v b(u) high-side bias voltage for u phase mosfet driving 26 v b(v) high-side bias voltage for v phase mosfet driving 27 v b(w) high-side bias voltage for w phase mosfet driving wh vh uh out(wl) out(vl) out(ul) (13) nu (17) w (16) v (14) u (21) pv (19) v s(w) (23), (23a) v s(v) (6) in_uh (7) in_vh (9) in_wh com (24), (24a) v s(u) out(uh) v dd out(vh) out(wh) vs(u) vs(v) vs(w) (5) v dd (8),(8a) com ul (10) in_ul vl (11) in_vl wl (12) in_wl /fo (1) /fo (2) v ts v ts cfod (3) cfod csc (4) csc (25) v b(u) (26) v b(v) vb(u) (27) v b(w) vb(v) vb(w) (15) nv (18) nw (22) pu (20) pw
FSB70625 motion spm? 7 series ?2013 fairchild semiconductor corporation 4 www.fairchildsemi.com FSB70625 rev. c0 electrical characteristics (t j = 25c, v dd = v bs = 15 v unless otherwise specified.) inverter part (each mosfet unless otherwise specified.) control part (each hvic unless otherwise specified.) 2nd notes: 1. bv dss is the absolute maximum voltage rating between drain and source terminal of each mosfet inside motion spm ? 7 product. v pn should be sufficiently less than this value considering the effect of the stray inductance so that v pn should not exceed bv dss in any case. 2. t on and t off include the propagation delay of the internal drive ic. listed values are measured at the laboratory test condition, and they can be different according to the field applications due to the effect of different printed circuit boards and wirings. please see figure 3 for the switching time defi nition with the switching test circuit of figure 4. 3. v ts is only for sensing-temperature of module and cannot shutdown mosfets automatically. 4. the fault-out pulse width t fod depends on the capacitance value of c fod according to the following approximate equation : c fod = 24 x 10 -6 x t fod [f] symbol parameter conditions min typ max unit bv dss drain - source breakdown voltage v in = 0 v, i d = 1 ma (2nd note 1) 250 - - v i dss zero gate voltage drain current v in = 0 v, v ds = 250 v - - 1 ma r ds(on) static drain - source turn-on resistance v dd = v bs = 15 v, v in = 5 v, i d = 1.0 a - 0.7 0.8 ? v sd drain - source diode forward voltage v dd = v bs = 15v, v in = 0 v, i d = -1.0 a - 0.9 1.2 v t on switching times v pn = 150 v, v dd = v bs = 15 v, i d = 1.0 a v in = 0 v ? 5 v, inductive load l = 3 mh low-side mosfet switching (2nd note 2) - 495 - ns t d(on) - 415 - ns t off - 370 - ns t d(off) - 275 - ns i rr -1.8- a t rr -70- ns e on -20- ? j e off -1.7- ? j symbol parameter conditions min typ max units i qdd quiescent v dd current v dd =15v, v in =0v v dd - com - 1.7 3.0 ma i qbs quiescent v bs current v bs =15v, v in =0v v b(x) -v s(x) ,v b(v) -v s(v) , v b(w) -v s(w) -4570 ? a i pdd operating v dd current v dd =15v,f pwm =20khz, duty=50%, pwm signal input for low side v dd - com - 1.9 3.2 ma i pbs operating v bs current v bs =15v,f pwm =20khz, duty=50%, pwm signal input for high side v b(u) -v s(u) ,v b(v) -v s(v) , v b(w) -v s(w) - 300 400 ? a uv ddd low-side undervoltage protection (figure 6) v dd undervoltage protection detection level 7.4 8.0 9.4 v uv ddr v dd undervoltage protection reset level 8.0 8.9 9.8 v uv bsd high-side undervoltage protection (figure 7) v bs undervoltage protection detection level 7.4 8.0 9.4 v uv bsr v bs undervoltage protection reset level 8.0 8.9 9.8 v v ts hvic temperature sens- ing voltage output v dd =15v, t hvic =25c (2nd note 3) 580 675 770 mv v ih on threshold voltage logic high level in - com --2.4v v il off threshold voltage logic low level 0.8 - - v v sc(ref) sc current trip level v dd =15v c sc - com 0.45 0.5 0.55 v t fod fault-out pulse width c fod =33nf (2nd note 4) 1.0 1.4 1.8 ms
FSB70625 motion spm? 7 series ?2013 fairchild semiconductor corporation 5 www.fairchildsemi.com FSB70625 rev. c0 recommended operating condition thermal resistance figure 2. recommended mcu interface and bootstrap circuit with parameters 3rd notes: 1. r ? jcb is simulation value with application board layout. (please refer user?s guide spm7 series) 2. parameters for bootsrap circuit elements are dependent on pwm algorithm. for 15 khz of switching frequency, typical example o f parameters is shown above. 3. rc coupling(r 5 and c 5 ) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. signal input of sp m ? is compatible with standard cmos or lsttl outptus. 4. bold lines should be short and thick in pcb pattern to have sma ll stray inductance of circuit, which results in the reduction o f surge voltage. symbol parameter conditions min. typ. max. unit v pn supply voltage applied between p and n - 150 200 v v dd control supply voltage applied between v dd and com 13.5 15.0 16.5 v v bs high-side bias voltage applied between v b and v s 13.5 15.0 16.5 v dv dd /dt, dv bs /dt control supply variation -1.0 - 1.0 v/ ? s t dead blanking time for preventing arm-short v dd = v bs = 13.5 ~ 16.5 v, t j ?? 150c 500 - - ns f pwm pwm switching frequency t j ?? 150c - 15 - khz symbol parameter conditions min. typ. max. unit r ? jcb junction to case bottom thermal resistance single mosfet operating condition (1st note 3) -1.2-c/w /fo v dd lin hin vb ho vs lo p n r 3 inverter output c 1 micom 15-v line 10 ? f one-leg diagram of spm these values depend on pwm control algorithm r 5 c 5 v pn c 2 v ts c 4 * example of bootstrap paramters: c 1 = c 2 = 1 ? f ceramic capacitor, com 5-v line c 3
FSB70625 motion spm? 7 series ?2013 fairchild semiconductor corporation 6 www.fairchildsemi.com FSB70625 rev. c0 figure 3. switching time definition figure 4. switching test circuit (low-side) figure 5. under voltage protection v ds i d v in t on t d(on) v in (o n ) 10% i d 90% i d 100% i d t rr 120% i d 0 v ds i d v in t off t d(o ff) v in (o f f ) 10% i d (a) turn-on (b) turn-off i rr 90% i d 15-v line 5-v line /fo v dd lin hin vb ho vs lo v ts com i d lv dc + v ds - uv bsd(ddd) uv bsr(ddr) input signal uv protection status high-side/low-side mosfet drain current reset detection reset fault output (only low-side uv protection)
FSB70625 motion spm? 7 series ?2013 fairchild semiconductor corporation 7 www.fairchildsemi.com FSB70625 rev. c0 figure 6. short-circuit current protection (with the external shunt resistance and cr connection) c1 : normal operation: mosfet on and carrying current. c2 : short circuit current detection (sc trigger). c3 : hard mosfet gate interrupt. c4 : mosfet turns off. c5 : fault output timer operation start : fault-out width (t fod ) c6 : input ?l? : mosfet off state. c7 : input ?h?: mosfet on state, but during the acti ve period of fault output the mosfet doesn?t turn on. c8 : mosfet off state figure 7. timing chart of interlock function control input output current sensing voltage of the shunt resistance fault output signal sc reference voltage cr circuit time constant delay sc protection circuit state set reset c6 c7 c3 c2 c1 c8 c4 c5 internal mosfet gate-source voltage hin lin ho lo
FSB70625 motion spm? 7 series ?2013 fairchild semiconductor corporation 8 www.fairchildsemi.com FSB70625 rev. c0 figure 8. temperature profile v ts vs. t hvic figure 9. example of application circuit 4th notes: 1. rc-coupling (r 5 and c 5 , r 2 and c 6 ) and c 1 , c 5 , c 7 , c 8 at each input of motion spm ? 7 product and mcu are useful to prevent improper input signal caused by surge-noise. 2. the voltage-drop across r 3 affects the low-side switching performance and the bootstrap characteristics since it is placed between com and the source ter minal of the low- side mosfet. for this reason, the voltage-drop across r 3 should be less than 1 v in the steady-state. 3. ground-wires and output terminals, should be thick and short in order to avoid surge-voltage and malfunction of hvic. 4. all the filter capacitors should be connected close to motion spm 7 product, and they should have good characteristics for r ejecting high-frequency ripple current. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 25 50 75 100 125 150 175 typ. 2.57v@125 typ. 2.10v@100 typ. 1.15v@50 1005 1255 505 hvic temperature, t hvic [ ] temperature sensing voltage, v ts [v] min. typ. max. wh vh uh out(wl) out(vl) out(ul) nu w v u p v s(w) v s(v) in_uh in_vh in_wh com v s(u) out(uh) vdd out(vh) out(wh) vs(u) vs(v) vs(w) v dd com ul in_ul vl in_vl wl in_wl /fo /fo v ts vts cfod cfod csc csc v b(u) v b(v) vb(u) v b(w) vb(v) vb(w) nv nw 5v 15v m mcu c 3 v dc r 3 r 2 c 6 c 2 c 4 c 7 r 5 c 8 c 1 c 5
FSB70625 motion spm? 7 series ?2013 fairchild semiconductor corporation 9 www.fairchildsemi.com FSB70625 rev. c0 detailed package outline drawings package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or data on the drawing and contact a fairchildsemicondu ctor representative to veri fy or obtain the most recent revision. package s pecifications do not expand the terms of fa irchild?s worldwide therm and conditions, specifically the the warranty therei n, which covers fairchild products. always visit fairchild semiconduct or?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg//pq/pqfn27a.pdf
FSB70625 motion spm? 7 series ?2013 fairchild semiconductor corporation 10 www.fairchildsemi.com FSB70625 rev. c0
FSB70625 motion spm? 7 series ?2013 fairchild semiconductor corporation 11 www.fairchildsemi.com FSB70625 rev. c0

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